Delta-sigma data converters or noise-shaping oversampling converters are preferred in many analog-to-digital conversion (ADC) applications because of their ability to exchange bandwidth and accuracy. For most of their history, delta-sigma converters were implemented as discrete-time architectures. More recently, continuous-time implementations are becoming preferred because of lower power consumption, reduced sensitivity to noise, and inherent anti-aliasing properties.
Most discrete-time implementations rely on switched-capacitor circuit techniques, and their loop coefficients are based on inherently accurate capacitor ratios. In contrast, for continuous-time delta-sigma converters, the loop coefficients are implemented as products of resistor (or transconductance) and capacitor values (RC-based time constants). These components are difficult to implement accurately during IC fabrication. It is common for RC products to vary by ±30% or more, while accuracies within ±5% are typically required to attain the desired performance targets. Therefore, a calibration technique is required for accurate control of these RC products.
One calibration technique used involved configuring an RC-based circuit as a relaxation oscillator. It requires a comparator as the only additional analog component. The frequency of oscillation depends on the RC product, and it is compared to an accurate reference frequency. The resistor or capacitor is implemented as a trimmable array, and its effective value can be adjusted, for example by a successive-approximation algorithm, until the oscillation frequency matches the reference frequency.